Since addition of binary numbers is common in a computer, it is desirable to perform this operation quickly. A typical adder is constructed from a plurality of logic gates with each gate introducing a delay to the operation. Because of the requirement to generate a carry bit when adding two numbers, the ripple or propagation delay increases with the number of bits in the numbers. For example, adding two digits and a carry bit requires a minimum delay path of two gates in order to generate both the digit and the next carry bit. If two n-bit numbers are added in this manner, a delay path of 2.sup.n gates would be anticipated. Such delays are obviously undesirable, particularly for large values of n.
It is possible to reduce the propagation delay. For example, logic arrays consisting of many logic gates can be designed to handle more than a single pair of digits simultaneously. A typical logic array, such as a 745283 chip with four full adders, adds two four bit binary numbers with a maximum delay path of three gates from the input of any gate to the carry bit. When such adders are cascaded to add larger numbers, the delay will increase. The delay path for two n-bit numbers is generally about 3n/4 gates. In general, the delay in adders is a function of the complexity and cost of the gating network used.
One application for adders in a computer is associated with first-in, first-out (FIFO) memory buffer designs. For example, one FIFO memory design employs four eight bit FIFO buffers which serve as a buffer between an eight bit and 32 bit data bus. Data that is received on the eight bit data bus is sequentially distributed to respective ones of the FIFO buffers. Data is read out of the FIFO buffers in parallel onto the 32 bit data bus. Conversely, data that is received on the 32 bit data bus is stored across all four FIFO buffers, and is read out sequentially from the buffers onto the eight bit data bus. Each FIFO buffer has a write and read pointer associated therewith to track the next location in the buffer where data is to be written to and read from, respectively. The difference between the write and read pointers is referred to as the count and represents the amount of memory space occupied within a FIFO buffer. The buffer counts have a particular relationship in that the greatest difference between the largest and smallest count will always be one or less. In order to know the total amount of data in all four buffers, the counts for each buffer must be added. The use of conventional adders for this operation would create the normal delays as discussed above.